This invention relates to time domain reflectometry (TDR), in particular, to a TDR tester in an integrated circuit (IC) for testing transmission lines.
Timely and accurate isolation of transmission line fault locations in a computer system is important, especially in a mission-critical system. Time domain reflectometers have been used in locating transmission line faults. Time Domain reflectometers measure transmission line impedance and determine if there is any discontinuity in the transmission line. TDR testing typically involves a step generator launching a fast edge into the transmission line under investigation through a resistor. The incident and reflected voltage waves are then monitored by a receiver, e.g., an oscilloscope, down stream from the resistor. This echoing technique reveals at a glance the characteristic impedance of the line under investigation in time domain and shows the position and nature (e.g., high or low impedance) of each discontinuity along the line under test. The location of each discontinuity may be calculated from the time delay.
FIG. 1 shows a typical TDR testing setup 100. A step generator 120 produces a positive-going incident wave Ei that is applied to a device 150 under test. The voltage step Ei travels down transmission line 152 at the velocity of propagation of transmission line 152. If load impedance ZL is equal to the characteristic impedance of transmission line 152, no wave is reflected and all that will be seen at high speed oscilloscope 110 is the incident voltage step Er recorded by a sample circuit 130 (observed wave shown in FIG. 2A). If a mismatch exists at load ZL, part of incident wave Ei is reflected. The reflected voltage wave Er will appear on the oscilloscope display algebraically added to the incident wave (observed wave shown in FIG. 2B). The reflected wave is readily identified since it is separated in time from the incident wave. This difference in time is used to determine the length of transmission line 152 from the monitoring point to the mismatch.
The waveform of the reflected wave reveals both the nature and magnitude of the mismatch. For example, for a transmitted voltage step shown in FIG. 2A, the reflected waveform for an open circuit is shown in FIG. 3A. FIG. 3B shows a reflected waveform for a short circuit. FIG. 3C shows a waveform for a load impedance that is twice the line impedance. FIG. 3D shows a waveform for a load impedance that is half the line impedance. FIGS. 4A, 4B, 4C and 4D show sample reflections produced by complex load impedances. For example, FIG. 4A shows a reflected waveform for a series R-L load; FIG. 4B shows a reflected waveform for a shunt R-C load; FIG. 4C shows a reflected waveform for a shunt R-L load; and FIG. 4D shows a reflected waveform for a series R-C load.
Conventionally, a computer system may include multiple printed circuit boards (PCBs). These PCBs are designed to be field-replaceable units (FRUs), such as backplanes 501, 502, 503 and 504 and centerplane 505, shown in FIG. 5. Each backplane 501, 502, 503 and 504 includes, for example, a built-in switch chip 501a that controls switching of various plug-in modules 501c, 501d and 501e in backplane 501 and a built-in control chip 501b for controlling communication with components on other backplanes, e.g., backplane 504. Backplanes 501, 502, 503 and 504 are connected to centerplane 505 which is a passive component, meaning that centerplane 505 simply contains couplers (e.g., compression mount connectors 505a, 505b, 505c and 505d) and no active components. Communication between the various backplanes 501, 502, 503, and 504 is accomplished through the centerplane 505. For example, communication between components 501b on backplane 501 and component 504a on backplane 504 is through a path 506 which includes a trace 506a between component 501b and connector 505a, trace 506b between connectors 505a and 505d, trace 506c between connector 505d and component 504a, and connectors 505a and 505d. Typically, each connector 505a, 505b, 505c and 505d includes multiple pins.
When there is a communication error between components 501b and 504a, the location of faults along path 506 are determined by trial-and-error, for example, by replacing one FRU at a time. Since centerplane 505 is passive, its failure rate is minimal. Hence, backplane 501 or backplane 504 is typically replaced first. Replacing a backplane is a laborious and time-consuming process, and causes great inconvenience to the users. Replacing a backplane can also be very expensive, especially for users who require uninterrupted service of the system.
A lab TDR machine may be used to locate faults along path 506. However, checking each and every connection manually during production is labor intensive and time consuming. In addition, it is often impractical for a service person to carry a lab TDR machine for troubleshooting a system that is up and running because lab TDR machines are expensive and relatively large in size. Furthermore, it is extremely difficult to access the components on a backplane because the backplane is typically buried inside a system. In addition, the pins/connectors on the boards are small and difficult to probe with probes which are of relatively large size. Therefore, locating faults along a path in an integrated circuit board using a lab TDR machine is impractical if not impossible.
The invention relates to method and apparatus for locating faults in transmission lines conveniently and accurately.
In accordance with the present invention, time domain reflectometer (TDR) testers are integrated into an integrated circuit (IC) to locate transmission line faults. In particular, a TDR tester is integrated into an integrated circuit for each transmitter that needs to be tested. Integration of multiple TDR testers into an integrated circuit allows convenient and accurate diagnosis of transmission line faults, thereby improving reliability prior to shipping of the system and improving first-time fix rate when a fault occurs during operation.
In one embodiment, an integrated circuit comprises a transmitter, a receiver, a path coupled between the transmitter and the receiver, and a TDR receiver for measuring a reflected signal from the path. The TDR receiver receives a variable reference signal.
In one embodiment, the TDR receiver may be a comparator which compares the reflected signal with the variable reference signal to generate an output signal. In one embodiment, an output terminal of the TDR receiver is coupled to a testing circuit which includes a sampling circuit for sampling the output signal at sampling instants determined by a timebase generator. In one embodiment, the timebase generator includes a signal generator, a coarse timebase circuit coupled to the signal generator and a fine timebase circuit coupled to the coarse timebase circuit. The coarse timebase circuit may include a plurality of delay units coupled to a first selector, the delay units being controlled by a clock. The fine timebase circuit may include a plurality of delay units coupled to a second selector.
In one embodiment, for each timebase value, the variable reference signal is varied over a predetermined range. When the output signal of the TDR receiver transitions from logic low to logic high, the reflected signal is approximately equal to the reference signal. A waveform is generated from the reflected signal as a function of time (against the timebase value). The waveform may then be analyzed against predetermined limits to determine whether there is a fault on the transmission line under test and the location of the fault.
In one embodiment, where the integrated circuit includes multiple transmission lines, each transmitter is integrated with a TDR receiver. A selector selects the transmission line under test.
This summary is not intended to limit the scope of the invention, which is defined solely by the claims attached hereto.